`timescale 1ns / 1ns
module tb_flow ();
    reg sys_clk;
    reg sys_rst_n;
    wire [1:0] flow_out;

    parameter MyPeriod = 20;

    // Test sequence
    initial begin
        sys_rst_n <= 1'b0;
        sys_clk<=1'b0;
        #100;
        sys_rst_n <= 1'b1;
        // #1000;
        // $stop;
    end

    always #(MyPeriod/2) sys_clk = !sys_clk;

    // Instantiate the flow module
    flow u_flow (
             .sys_clk(sys_clk),
             .sys_rst_n(sys_rst_n),
             .flow_out(flow_out)
         );


endmodule
